This invention relates to field-effect transistor logic circuitry and more particularly, to such circuits containing a pair of serial inverters.
The basic field-effect transistor, or FET, inverter consists essentially of a load FET and an input FET. The load FET serves essentially as a resistor connected between a supply voltage and a common node. The input FET whose drain-source path is connected between the common node and a circuit reference point acts as a switch. As is well-known, one particular type of field-effect transistor is the metal-oxide-semiconductor FET known generally as a MOSFET and all FETS referred to hereinafter are assumed P-channel MOSFET devices of the enhancement mode type, but it is understood that N-channel depletion mode MOSFET devices, or other types of transistors are equally applicable.
In the basic FET inverter the input is applied to the gate of the input FET, and a ground input, defined, for instance, as a logical 0, causes the input FET to be non-conductive; thus, the fixed voltage provided at the common node by the load FET represents the inversion of the input. A negative input sufficient to cause the input FET to become conductive is defined as the opposite logic state or logical 1. This input grounds the common node providing a logical 0. The output level is determined by the supply voltage so that the inverter can also provide amplification.
In some logic applications, two serially connected inverters are required, such as where the circuit functions as a preamplifier for a push-pull amplifier. All FET inverters exhibit an inherent delay and where a serial pair of inverters is utilized, both contribute to the total delay. Since the speed of the logic circuit is often of paramount importance, this combined delay is unacceptable in many circumstances. Therefore improvements in the speed of inverter operation have been suggested. For instance, an inverter may be provided with a bootstrap capacitor coupling the gate of its load FET to the common node. The resultant capacitive feedback causes the voltage of the gate of the load FET to approximately follow the voltage at the common node, thereby maintaining a nearly constant current through the load FET during the voltage transition at the common node. This speeds up the transition because there is no opposing current change as there would be without the bootstrapping. A single bootstrap inverter is disclosed, for instance, in FIG. 1 of R. W. Polkinghorn et al. Re 27,305, issued Mar. 14, 1972, and it may, of course, be serially coupled to another inverter as shown in FIG. 1 hereof.
However, transition speed of a pair of serial inverters in which the inverters are individually bootstrapped may still not be sufficient since the second of the inverters must await the change of state of the preceding inverter and this serial delay is not compensated for by the bootstrapping of either inverter. Furthermore, bootstrapping each inverter complicates the circuit since an isolating FET as well as the capacitor is required to bootstrap each inverter.
It is therefore an object of the present invention to provide a fast-acting logic circuit.
It is a further object to provide a fast-acting, serial inverter circuit which compensates for serial delay.
It is also an object to provide a fast-acting, amplifier which provides two serial inversions.
It is still a further object to provide a fast-acting serial inverter circuit utilizing field-effect transistors of the metal-oxide-semiconductor type.